Characteristic curves for the JFET are shown below. The application of a voltage Vds from drain to source will cause electrons to flow through the channel. It can be seen that for a given value of Gate voltage, the current is nearly constant over a wide range of Source-to-Drain voltages.
But, when the Gate is made more negative, it depletes the majority carriers from a larger depletion zone around the gate reducing the current flow for a given value of Source-to-Drain voltage.
Let us assume that Vgs= 0V (at this point of time gate is shorted to the source).
Changing the Gate voltage modulates the current flow through the device.
Now, if Vds is increased, drain current will also increase linearly and at some voltage between 2V to 6V, a saturation effect occurs and a "knee" develops in the characteristic curves.
As drain current is increased, drain-to-source voltage also increases until avalanche effect due to diode breakdown takes place.
Now, if gate voltage is introduced by making gate negative with respect to the source and the drain-to-source voltage is varied from zero up to breakdown, the curve is of similar shape but shifted down. This happens because negative voltage on the gate has reduced drain current.
However, in case of P-channel type, in which holes (positive) are major current carriers application of positive gate could do the job of repelling holes.
The transfer characteristic for the JFET could be used for visualising the gain from the device and identifying the region of linearity. Hence, the gain is proportional to the slope of the transfer curve. The current value IDSS represents the value when the Gate is shorted to ground, which is the maximum current for the device. The Gate voltage at which the current becomes zero is called the "pinch voltage", VP. Note that the dashed line represents the gain in the linear region of operation that touches the zero current line at about half the pinch voltage.